--
-- VHDL Architecture test.control2.behav
--
-- Created:
--          by - toban963.student (southfork-15.edu.isy.liu.se)
--          at - 17:06:24 10/07/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY stimuli_keyboard IS
   PORT( 
      kb_clk  : OUT    std_logic;   -- keyboard clock
      kb_data : OUT    std_logic;   -- scan code bits
      sys_clk : OUT    std_logic
   );

-- Declarations

END stimuli_keyboard ;

--
ARCHITECTURE behav OF stimuli_keyboard IS
    TYPE key12x11 IS ARRAY (0 TO 11) OF std_logic_vector(10 DOWNTO 0);
    SIGNAL temp_kb_clk: std_logic;
BEGIN
  -- sys_clk
  PROCESS
    BEGIN
    sys_clk <= '1';
    wait for 10 ns;
    sys_clk <= '0';
    WAIT FOR 10 ns;
  END PROCESS;
  
  
  --kb_data and kb_clk
  PROCESS
    CONSTANT keys: key12x11 := 
    ("11001010101", "11000111011", "11000101101", "11000111011", "11000111001", "11001010101", "11000110111", 
    "11000110111","11000111101", "11000110111", "11000111011", "11000110111"); 
    -- end&P&(KEY)&start, V->W->1->W->A->V->S->S->2->S->W->S
    BEGIN
      for x in 0 to 11 LOOP
        WAIT FOR 50 us;
        FOR i in 0 TO 10 LOOP
          kb_data <= keys(x)(i) after 10 ns;
          kb_clk <= '0' after 2500 ns, '1' after 5000 ns;
      
          WAIT FOR 5 us;
          temp_kb_clk <= '1';
        END LOOP;
      END LOOP;
           
  END PROCESS;


END ARCHITECTURE behav;